Publications in refereed proceedings
Walters, III, E. G., and Schulte, M. J., “Fast, Bit-accurate Simulation of Truncated-Matrix Multipliers and Squarers,” Proceedings, Forty-Fourth Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 2010.
Walters, E. G., and Schulte, M. J., “Efficient Function Approximation Using Truncated Multipliers and Squarers,” Proceedings, 17th IEEE Symposium on Computer Arithmetic, IEEE Computer Society Press, pp. 232-239, Cape Cod, MA, June 2005.
Walters, E. G., Schulte, M. J., and Arnold, M. G., “Truncated Squarers with Constant and Variable Correction,” Proceedings, SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XIV, vol. 5559, pp. 40-50, Denver, CO, August 2004.
Walters, E. G., Glossner, J., and Schulte, M. J., “Automatic VHDL Model Generation of Parameterized FIR Filters,” Domain Specific Processors: Systems Architectures, Modeling, and Simulation, Signal Processing and Communications Series, pp. 1-17, Marcel Dekker, NY, November 2003.
Walters, E. G., Arnold, M.G., and Schulte, M. J., “Using Truncated Multipliers in DCT and IDCT Hardware Accelerators,” Proceedings, SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, vol. 5205, pp. 573-584, San Diego, CA, August 2003.
Schulte, M. J., Marquette, L. P., Krithivasan, S., Walters, E. G., and Glossner, J., “Combined Multiplication and Sum of Squares Units,” [One of three finalists for best paper award] Proceedings, IEEE International Conference on Application-Specific Systems, Architectures, and Processors, the Hague, Netherlands, IEEE Computer Society Press, pp. 204-214, June 2003.
Walters, E. G., and Schulte, M. J., “Design Tradeoffs Using Truncated Multipliers in FIR Filter Implementations,” Proceedings, SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XII, vol. 4791, pp. 357-368, Seattle, WA, July 2002.
Walters, E. G., Schlessman, J., and Schulte, M. J., “Combined Unsigned and Two’s Complement Hybrid Squarers,” Proceedings, Thirty-Fifth Asilomar Conference on Signals, Systems, and Computers, IEEE Press, pp. 861-866, Pacific Grove, CA, November 2001.
